1. Field of the Invention
The present invention relates to formation of an electrode in a semiconductor switching device such as a JFET, an SIT, a MOSFET, and an IGBT.
2. Description of the Background Art
Semiconductor switching devices responsible for a switching operation and used in power sources and other electrical instruments include JFETs, SITs, MOSFETs, and IGBTs. In such semiconductor switching devices, an effective area to house a cell is an important parameter to determine characteristics and cost, and is required to be increased.
Meanwhile, a region directly under an electrode pad is an invalid region (see Japanese Patent Application Laid-Open No. 2007-42817). In order to enhance characteristics and realize cost reduction, the invalid region directly under the electrode pad should be used as a valid region.
Assembly techniques intended to enhance power cycle performance or heat dissipation performance include direct lead bonding (DLB, see Japanese Patent Application Laid-Open No. 2007-142138) of an emitter electrode and pressure bonding. Meanwhile, an emitter electrode may be divided by wiring of a gate interconnect line to suppress gate delay. This structure however becomes an obstacle to the application of the aforementioned assembly techniques.